Semiconductor devices include deep-submicron metal-oxide semiconductor fieldeffect transistors (MOSFET). FIG. 1 illustrates a conventional cell of a MOSFET. The cell 100 comprises a gate 102 on a substrate 104. The gate typically comprises a polysilicon layer 106 with a salicide layer 108 on top. Sidewall spacers 110 comprising oxide protect the gate 106. The cell 100 also comprises a salicide layer 112 and a silicon nitride layer 114 on the substrate 104 next to the spacers 110. In the substrate 104 on the source and drain sides are extensions 116, halo implanted areas 118, and the source 120 and drain 122 regions. The cell 100 has a lateral symmetric channel doping profile. However, as device dimensions are scaled down to the sub-100 nm regime, the speed of the device is not scaled in the same manner.
Accordingly, there exists a need for a method of fabrication of a submicron MOSFET which improves the speed of the device. The present invention addresses this need.